FIG. 3 of patent document 1 listed below discloses the configuration of a “CDS circuit 3a” that corresponds to a single column of a “pixel unit 20”.
The “CDS circuit 3a” is provided with a “sample and hold switch sw1” that controls the input of the image signal output from the “pixel unit 20”. One end of a “capacitor (sample and hold capacitor) C31” for holding the image signal is connected to the output side of the “sample and hold switch sw1”. Furthermore, a “ramp signal supply source 31a” is connected to the other end of the “capacitor C31”, which is the end opposite to the end connected to the “sample and hold switch sw1”. The “ramp signal supply source 31a” supplies a ramp signal for changing the electric potential of the image signal held by the “capacitor C31”.
Furthermore, a “node n1” that connects the “sample and hold switch sw1” and the “capacitor C31” is connected to the non-inverting input terminal of a “differential amplifier 33a”. Moreover, a “capacitor C32” is provided between the inverting input terminal and the GND. A “clamp switch sw2” is provided between the output terminal of the “differential amplifier 33a” and a “connection node n2” that connects the inverting input terminal and the “capacitor C32”.